1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a dynamic random access memory (DRAM) cell storage node.
2. Description of the Related Art
Dynamic random access memory (DRAM) devices may be divided into a stack type, a trench type, and other types. The trench type is chiefly used in high integration DRAM devices. Accordingly, the present invention will be described in view of a stack type capacitor.
Elements constituting DRAM devices have been gradually scaled down in size to achieve high integration in DRAM devices. Due to this size reduction, it is very difficult to maintain the required capacitance of the capacitors used for data storage in DRAM devices and perform the photo and etching processes to form the elements. Misalignment of sequentially formed elements in a DRAM is a common problem.
FIG. 1A to FIG. 1C sequentially illustrate the process steps of forming a DRAM device where misalignment has occurred. First, referring to FIG. 1A and FIG. 1B, an interlayer insulating film 14 including bit lines 16 formed on a semiconductor substrate 10 is penetrated, so that buried contacts (i.e., storage contact plugs) 18 are formed. The storage contact plugs 18 are electrically connected to the semiconductor substrate 10 between shallow trenches 12. Then, a polysilicon layer 20 is formed on the interlayer insulating film 14 to form the storage nodes (e.g., stack type capacitors).
Referring to FIG. 1C, a mask (not shown) is formed on the polysilicon layer 20 using a photo-etching process in order to define a storage node formation region. The storage nodes 20a are formed using a polysilicon layer etching process using the mask. To increase the efficient surface area of the storage nodes 20a, a hemispherical grain (HSG) layer is formed on the surface areas thereof. Then, to form the storage node capacitors, a capacitor formation dielectric film (not shown) is deposited on the insulating layer 14 and the storage nodes 20a, and a conductive layer (not shown) is deposited to form upper electrodes.
In the foregoing method, if the mask is misaligned with the storage contact plugs 18, a few problems may be generated. The etching process of the polysilicon layer 20 conventionally includes overetching of the polysilicon to prevent electrical bridging between storage nodes 20a. As a result, the polysilicon of the upper region of the storage contact plugs 18 is etched during this overetching if there is any misalignment. In addition, the interlayer insulating film 14 connected to the storage nodes 20a is etched by the cleaning material used in subsequent cleaning processes. As a result, the area of contact between a storage node 20a and a storage contact plug 18 and the interlayer insulating film 14 is reduced. This reduction of contact area generates increased resistance and may result in the collapse or breakage of the storage node 20a during subsequent processing. These problems become severe in high integration DRAM devices, and are inevitable in very large scale integration (VLSI) devices such as 1Gbit DRAM devices.
One of the methods for solving these problems is to form the storage node using a damascene process. Referring to FIG. 2A to FIG. 2C, a first insulating layer 54 including bit lines 56 formed on a semiconductor substrate 50 is penetrated to form storage contact plugs 60 which are electrically connected to the semiconductor substrate 50 between trenches 52. It should be noted that FIG. 2A to FIG. 2C show an etch stop layer 58 which is not used in this method, but is used in a variation of this method described below.
Then, a second insulating layer 62 is formed on the first insulating layer 54. The second insulating layer 62 is partially etched to form openings and to expose the top surfaces of the storage contact plugs 60 for formation of the storage nodes 64. After forming the storage nodes 64 by filling the openings with polysilicon, the surface area of the storage nodes 64 is exposed by etching the second insulating layer 62 around the storage nodes 64. This process must be controlled to achieve the required capacitance of the capacitor being formed.
However, this method has a few problems. The capacitance of the capacitors formed by the method varies according to the quantity of the second insulating layer 62 that is etched on the sides of the storage node 64 by the conventional wet etch or dry etch in the etching process. Further, if the second insulating layer 62 is overetched, a bit line which is in a peripheral circuit region of the DRAM device may be exposed to attack during subsequent formation of the upper electrodes.
Referring again to FIG. 2A to FIG. 2C, a variation on the above process for forming a storage node is shown in the case of a misalignment. Referring to FIG. 2A, an insulating etch-stop layer 58, whose etch selectivity is high with respect to an oxide layer such as a silicon nitride layer, is generally formed on the first insulating layer 54, before or after formation of storage contact plugs 60.
As shown in FIG. 2B to FIG. 2C, the storage node formation region is misaligned with the storage contact plugs 60. As a result, when the storage nodes 64 are formed the first insulating layer 54 may be partially etched in the upper region of the storage contact plugs 60. Etchant may penetrate along the interface between the storage nodes 64 and the etch stop layer 58, so that a recessed region is created, as shown in FIG. 2C. As a result, dielectric leakage of the capacitors and defective step coverage of an upper electrode may occur, and reliability of the DRAM device is reduced.